Abstract

Two issues about voice conversion are presented. The first issue is conversion of speaking voice into singing voice, which is an important issue to investigate how singing-voices are perceived and generated, as a part of studies of non-linguistic information in speech sounds. Since most speech synthesis methods were not proposed for singing-voice synthesis but for spoken-voice synthesis, it is impossible to reveal how singing-voices are perceived and generated by using these methods. This talk shows the possibility of synthesizing a singing-voice by adding non-linguistic information into speaking voice. The second issue is conversion of neutral speech into expressive speech. Much of the earlier work has focused on the relationship between emotional speech and acoustic features that is characterized by statistics. The problem is that there lacks a model which takes the aspects of vagueness and human perception into consideration. In this talk, a three-layer model for the perception of emotional speech is introduced, that is, the topmost layer: five categories of emotion; the middle layer: human perceptual aspect; and the bottommost layer: acoustic features. Some demonstrations of synthesizing emotional speech are presented, using the perception model of emotional speech and a new voice conversion method based on temporal decomposition.

Prof. Masato Akagi received the B.E. degree in electronic engineering from Nagoya Institute of Technology in 1979, and the M.E. and the Ph.D. Eng. degrees in computer science from Tokyo Institute of Technology in 1981 and 1984. In 1984, he joined the Electrical Communication Laboratory, Nippon Telegraph and Telephone Corporation (NTT). From 1986 to 1990, he worked at the ATR Auditory and Visual Perception Research Laboratories. Since 1992, he has been with the School of Information Science , JAIST, where he is currently a professor. His research interests include speech perception mechanisms of human beings, and speech signal processing. Dr. Akagi received the IEICE Excellent Paper Award from the Institute of Electronics, Information and Communication Engineers (IEICE) in 1987, and the Sato Prize for Outstanding Paper from the Acoustical Society of Japan (ASJ) in 1998 and 2005. He is currently a vice-president of the ASJ.

Abstract

Wireless multihop networks formed by wireless access points with decentralized control receive attentions for the novel cost effective network technology. One of promising deployment among them is called wireless mesh networks, where multiple stationary wireless access points form multihop broadband backbone network for mobile terminals. Wireless mesh networks can cooperate with existing cellular network or wireless LAN to extend coverage area of them. Due to the shared use of limited wireless bandwidth and the need for support of mobile terminals, wireless mesh networks have some technical challenges especially in MAC protocols, routing protocols. This tutorial presents the overview of concepts, architecture and protocols of wireless mesh networks. In the data link layer, multiple access protocols for distributed fairness and QoS control, and capacity improvement by multiple channel configuration schemes are described. In the network layer, routing protocols are discussed in terms of the design of high throughput link metrics, terminal handover support, interconnections with the Internet and so on. From aspects of reliable end-to-end packet transport in the wireless environment, cross layer design issues are discussed. From viewpoints of network services, wireless mesh networks are expected to providing people with as local community network services, such as environmental information gathering and notification service after the occurrence of disasters. Recent researches on test beds and experiments aiming to realize these services are presented.
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Abstract

Session 1: IMS Basics, Architecture, and Standards

• IMS motivation – Internet plus Telecommunications = Value added Internet?
• IMS Drivers - Applications: Fixed Mobile Convergence, NGN, Triple Play, IPTV, Web2.0
• IMS Architecture Principles
• IMS Core Layer Key interfaces and interactions
• IMS Application Layer Server Options (CAMEL, OSA, SIP AS)
• Service Provisioning in the IMS – IMS Integration with SDPs and OSS/BSS
• IMS Standard Review - 3GPP IMS, 3GPP2 MMD, ETSI TISPAN NGN, Packet Cable IMS, A-IMS
• Towards IMS Tools and Testbeds: Open Source IMS and Open IMS Playground ( www.open-ims.org )

Session 2: IMS and IPTV: Towards Interactive TV and Media Services

• IPTV Standards and IPTV Implementation Options
• IMS-based IPTV Architecture – Integrating communications and media delivery
• Service Examples and features for IMS-based IPTV – the “Virtual Sofa”
• Experiences and prototypes from the FOKUS Media Interoperability Lab (www.mediainteroperabilitylab.org)

Session 3: Questions & Answers

Abstract

Wireless transmission is often error prone due to multipath fading. It is now well known that multiple antennas can greatly increase the capacity and reliability of a wireless communication link in a fading environment. In a nutshell, the independent paths or channels between the transmit and receive antennas provide spatial diversity, which can be exploited by well-designed space–time coding techniques. Achieving spatial diversity, however, requires multiple antennas be placed sufficiently far apart, which can be problematic for size-limited communication terminals.

Abstract

The concept of shrinking semiconductor device dimensions has been the mainstay of CMOS Integrated circuit over many generations of technology since 1968 and continues today relatively unabated. However, the International Technology Roadmap for Semiconductors (ITRS) highlights major challenges in the continued shrinking of the classical planar CMOS transistor. The 2005 ITRS had identified numerous issues currently without known solutions - so called "red brick wall" – thus making it difficult for semiconductor communities to generate or define device specification and ultimately difficult to continue Moore Law.

Some of the major issues associated with shrinking device dimensions include accurate nanometer gate length control, off-state current leakage resulting in increased power consumption, insulator thickness of atomic dimensions and its associated current leakage, degraded carrier mobility, random dopant fluctuations etc.

With these challenges in mind, scientists have made much progress in recent years to overcome the scaling limitations of classical planar CMOS transistors and maintain historical performance trend. New innovations are pushing CMOS transistors to their ultimate limits, beyond any previous predictions, to effectively meeting the incessant demand for higher density, performance, power and most importantly at lower cost.

This presentation will discuss the development progress and implication of novel material and device architecture for scaling semiconductor devices into Nanometer Era

Abstract

Over the past several years FPGA technology has advanced rapidly, to the point where FPGA chips are now used to implement entire high-performance digital systems. Today's most advanced FPGA devices can implement millions of equivalent logic gates, may contain megabytes of memory cells, and support serial communications standards above 1 GHz. FPGAs are widely used in many industries, including consumer equipment, automotive, medical and industrial test, computers and storage, video processing and broadcasting, and wireless and wired communications equipment. FPGAs are now found in almost all digital electronics equipment produced around the world.

This tutorial gives an overview of FPGA technology, including both the low-cost (tens of dollars) and high-performance (thousands of dollars) FPGA chips available, and the many types of CAD tools that are provided to aid in the design process. CAD tools covered will include the traditional back-end place and route solutions, as well as the more advanced system-level tools that allow designers to more quickly piece together circuits by making use of predeveloped intellectual property cores. The tutorial will also describe the research challenges facing FPGA manufacturers, including power, performance, and usability, and will show how the manufacturers are continuing to find innovative solutions to these issues.

The tutorial will describe Altera FPGA and CAD technology as an example of a leading technology driver--Altera Corporation offers the highest performance FPGAs in the industry, as well as world-leading low-cost FPGA devices. Altera CAD tools are also world-class and offer the simplest interface that encourages high productivity. Finally, the training material available in Altera's world-leading University Program will be described, as it provides a simple yet powerful means of introducing new designers to the exciting world of FPGA technology.

Abstract

Four types of single layer waveguide arrays are developed in Tokyo Tech. Key features as well as the advantages in terms of fabrication costs have been demonstrated. Millimetre wave test systems, utilizing these antennas are now developed in Tokyo Tech Oookayama campus. It is a project, which covers CMOS technology as well.

1. ANTENNAS –BASIC STUDY

Basic theory for antenna engineering will be briefly summarized. Unique feature of waveguide arrays are explained for millimeter wave wireless systems. Modelling of electrically large structures into the canonical problems is also mentioned.

2. SINGLE-LAYER WAVEGUIDE SLOT ARRAYS

We have developed single mode waveguides and oversized waveguides for potentially mass producible planar arrays. These arrays can cover very high gain ranging up to 35 dBi which is not attainable by planar arrays using microstrip and triplate with larger line loss. The high potential of the single-layer waveguide arrays in high gain and high frequency applications is fully demonstrated. Four types of the arrays are designed, measured and commercialized. These are,

3. SYSTEM APPLICATION AND TOKYO TECH WIRELESS FIBER PROJECT

System applications of the waveguide arrays are presented. The large scale project “RF Coexisting Technology on High Speed Baseband IC for Millimeter Wave Radio Systems” is supported by Ministry of Internal Affairs and Communications (MIC) funding as well as Industry’s participation. It started in FY2007 and will run until FY2011. The objective of this project is to develop RF coexisting technology on high speed baseband CMOS for Millimeter wave radio systems. Outdoor and indoor millimeter wave radio communication systems beyond Gbps are designed based upon these ICs, the former of which will be demonstrated in Tokyo Tech Ookayama campus.